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Journal of the American Chemical Society Nov 2023Programmable biomolecule-mediated computing is a new computing paradigm as compared to contemporary electronic computing. It employs nucleic acids and analogous... (Review)
Review
Programmable biomolecule-mediated computing is a new computing paradigm as compared to contemporary electronic computing. It employs nucleic acids and analogous biomolecular structures as information-storing and -processing substrates to tackle computational problems. It is of great significance to investigate the various issues of programmable biomolecule-mediated processors that are capable of automatically processing, storing, and displaying information. This Perspective provides several conceptual designs of programmable biomolecule-mediated processors and provides some insights into potential future research directions for programmable biomolecule-mediated processors.
PubMed: 37864571
DOI: 10.1021/jacs.3c04142 -
Seminars in Hearing May 2021This case study examines the methods used to troubleshoot a cochlear implant processor via video visit with a nonagenarian (90+ years old) with a bimodal cochlear... (Review)
Review
This case study examines the methods used to troubleshoot a cochlear implant processor via video visit with a nonagenarian (90+ years old) with a bimodal cochlear implant system. This article will discuss the evaluation and management as well as which specific issues could be addressed virtually and how they were resolved. Examples will be provided about how to virtually connect with the patient and how to best facilitate communication during a video visit. Additionally, this article will examine the captioning apps and other hearing assistive technology available for smartphones that can provide further assistance during a cell phone call along with their benefits and limitations.
PubMed: 34381294
DOI: 10.1055/s-0041-1731691 -
Ear and HearingBilateral cochlear implant (BiCI) listeners use independent processors in each ear. This independence and lack of shared hardware prevents control of the timing of...
The Impact of Synchronized Cochlear Implant Sampling and Stimulation on Free-Field Spatial Hearing Outcomes: Comparing the ciPDA Research Processor to Clinical Processors.
OBJECTIVES
Bilateral cochlear implant (BiCI) listeners use independent processors in each ear. This independence and lack of shared hardware prevents control of the timing of sampling and stimulation across ears, which precludes the development of bilaterally-coordinated signal processing strategies. As a result, these devices potentially reduce access to binaural cues and introduce disruptive artifacts. For example, measurements from two clinical processors demonstrate that independently-running processors introduce interaural incoherence. These issues are typically avoided in the laboratory by using research processors with bilaterally-synchronized hardware. However, these research processors do not typically run in real-time and are difficult to take out into the real-world due to their benchtop nature. Hence, the question of whether just applying hardware synchronization to reduce bilateral stimulation artifacts (and thereby potentially improve functional spatial hearing performance) has been difficult to answer. The CI personal digital assistant (ciPDA) research processor, which uses one clock to drive two processors, presented an opportunity to examine whether synchronization of hardware can have an impact on spatial hearing performance.
DESIGN
Free-field sound localization and spatial release from masking (SRM) were assessed in 10 BiCI listeners using both their clinical processors and the synchronized ciPDA processor. For sound localization, localization accuracy was compared within-subject for the two processor types. For SRM, speech reception thresholds were compared for spatially separated and co-located configurations, and the amount of unmasking was compared for synchronized and unsynchronized hardware. There were no deliberate changes of the sound processing strategy on the ciPDA to restore or improve binaural cues.
RESULTS
There was no significant difference in localization accuracy between unsynchronized and synchronized hardware (p = 0.62). Speech reception thresholds were higher with the ciPDA. In addition, although five of eight participants demonstrated improved SRM with synchronized hardware, there was no significant difference in the amount of unmasking due to spatial separation between synchronized and unsynchronized hardware (p = 0.21).
CONCLUSIONS
Using processors with synchronized hardware did not yield an improvement in sound localization or SRM for all individuals, suggesting that mere synchronization of hardware is not sufficient for improving spatial hearing outcomes. Further work is needed to improve sound coding strategies to facilitate access to spatial hearing cues. This study provides a benchmark for spatial hearing performance with real-time, bilaterally-synchronized research processors.
Topics: Cochlear Implantation; Cochlear Implants; Computers, Handheld; Hearing; Humans; Sound Localization; Speech Perception
PubMed: 34882619
DOI: 10.1097/AUD.0000000000001179 -
Sensors (Basel, Switzerland) Dec 2021The leakage of hazardous gases and chemical vapors is considered one of the dangerous accidents that can occur in laboratories, workshops, warehouses, and industrial... (Review)
Review
The leakage of hazardous gases and chemical vapors is considered one of the dangerous accidents that can occur in laboratories, workshops, warehouses, and industrial sites that use or store these substances. The early detection and alarming of hazardous gases and volatile chemicals are significant to keep the safety conditions for the people and life forms who are work in and live around these places. In this paper, we investigate the available mobile detection and alarming systems for toxic, hazardous gases and volatile chemicals, especially in the laboratory environment. We included papers from January 2010 to August 2021 which may have the newest used sensors technologies and system components. We identified (236) papers from Clarivate Web of Science (WoS), IEEE, ACM Library, Scopus, and PubMed. Paper selection has been done based on a fast screening of the title and abstract, then a full-text reading was applied to filter the selected papers that resulted in (42) eligible papers. The main goal of this work is to discuss the available mobile hazardous gas detection and alarming systems based on several technical details such as the used gas detection technology (simple element, integrated, smart, etc.), sensor manufacturing technology (catalytic bead, MEMS, MOX, etc.) the sensor specifications (warm-up time, lifetime, response time, precision, etc.), processor type (microprocessor, microcontroller, PLC, etc.), and type of the used communication technology (Bluetooth/BLE, Wi-Fi/RF, ZigBee/XBee, LoRa, etc.). In this review, attention will be focused on the improvement of the detection and alarming system of hazardous gases with the latest invention in sensors, processors, communication, and battery technologies.
Topics: Gases; Humans; Laboratories
PubMed: 34884132
DOI: 10.3390/s21238128 -
Sensors (Basel, Switzerland) Sep 2019It is widely recognized that nanoscience and nanotechnology and their subfields, such as nanophotonics, nanoelectronics, and nanomechanics, have had a tremendous impact... (Review)
Review
It is widely recognized that nanoscience and nanotechnology and their subfields, such as nanophotonics, nanoelectronics, and nanomechanics, have had a tremendous impact on recent advances in sensing, imaging, and communication, with notable developments, including novel transistors and processor architectures. For example, in addition to being supremely fast, optical and photonic components and devices are capable of operating across multiple orders of magnitude length, power, and spectral scales, encompassing the range from macroscopic device sizes and kW energies to atomic domains and single-photon energies. The extreme versatility of the associated electromagnetic phenomena and applications, both classical and quantum, are therefore highly appealing to the rapidly evolving computing and communication realms, where innovations in both hardware and software are necessary to meet the growing speed and memory requirements. Development of all-optical components, photonic chips, interconnects, and processors will bring the speed of light, photon coherence properties, field confinement and enhancement, information-carrying capacity, and the broad spectrum of light into the high-performance computing, the internet of things, and industries related to cloud, fog, and recently edge computing. Conversely, owing to their extraordinary properties, 0D, 1D, and 2D materials are being explored as a physical basis for the next generation of logic components and processors. Carbon nanotubes, for example, have been recently used to create a new processor beyond proof of principle. These developments, in conjunction with neuromorphic and quantum computing, are envisioned to maintain the growth of computing power beyond the projected plateau for silicon technology. We survey the qualitative figures of merit of technologies of current interest for the next generation computing with an emphasis on edge computing.
PubMed: 31546907
DOI: 10.3390/s19184048 -
Philosophical Transactions. Series A,... Oct 2017There is a broad design space for concurrent computer processors: they can be optimized for low power, low latency or high throughput. This freedom to tune each...
There is a broad design space for concurrent computer processors: they can be optimized for low power, low latency or high throughput. This freedom to tune each processor design to its niche has led to an increasing diversity of machines, from powerful pocketable devices to those responsible for complex and critical tasks, such as car guidance systems. Given this context, academic concurrency research sounds notes of both caution and optimism. Caution because recent work has uncovered flaws in the way we explain the subtle memory behaviour of concurrent systems: specifications have been shown to be incorrect, leading to bugs throughout the many layers of the system. And optimism because our tools and methods for verifying the correctness of concurrent code-although built above an idealized model of concurrency-are becoming more mature. This paper looks at the way we specify the memory behaviour of concurrent systems and suggests a new direction. Currently, there is a siloed approach, with each processor and programming language specified separately in an incomparable way. But this does not match the structure of our programs, which may use multiple processors and languages together. Instead we propose a approach, where program components carry with them a description of the sort of concurrency they rely on, and there is a mechanism for composing these. This will support not only components written for the multiple varied processors found in a modern system but also those that use idealized models of concurrency, providing a sound footing for mature verification techniques.This article is part of the themed issue 'Verified trustworthy software systems'.
PubMed: 28871054
DOI: 10.1098/rsta.2015.0406 -
Biomedical Engineering Letters May 2022Conventional spike sorting and motor intention decoding algorithms are mostly implemented on an external computing device, such as a personal computer. The innovation of...
Conventional spike sorting and motor intention decoding algorithms are mostly implemented on an external computing device, such as a personal computer. The innovation of high-resolution and high-density electrodes to record the brain's activity at the single neuron level may eliminate the need for spike sorting altogether while potentially enabling in vivo neural decoding. This article explores the feasibility and efficient realization of in vivo decoding, with and without spike sorting. The efficiency of neural network-based models for reliable motor decoding is presented and the performance of candidate neural decoding schemes on sorted single-unit activity and unsorted multi-unit activity are evaluated. A programmable processor with a custom instruction set architecture, for the first time to the best of our knowledge, is designed and implemented for executing neural network operations in a standard 180-nm CMOS process. The processor's layout is estimated to occupy 49 mm of silicon area and to dissipate 12 mW of power from a 1.8 V supply, which is within the tissue-safe operation of the brain.
PubMed: 35529345
DOI: 10.1007/s13534-022-00217-z -
Sensors (Basel, Switzerland) Sep 2022The TrustZone technology is incorporated in a majority of recent ARM Cortex A and Cortex M processors widely deployed in the IoT world. Security critical code execution...
The TrustZone technology is incorporated in a majority of recent ARM Cortex A and Cortex M processors widely deployed in the IoT world. Security critical code execution inside a so-called secure world is isolated from the rest of the application execution within a normal world. It provides hardware-isolated area called a trusted execution environment (TEE) in the processor for sensitive data and code. This paper demonstrates a vulnerability in the secure world in the form of a cross-world, secure world to normal world, covert channel. Performance counters or Performance Monitoring Unit (PMU) events are used to convey the information from the secure world to the normal world. An encoding program generates appropriate PMU event footprint given a secret . A corresponding decoding program reads the PMU footprint and infers using machine learning (ML). The machine learning model can be trained entirely from the data collected from the PMU in user space. Lack of synchronization between PMU start and PMU read adds noise to the encoding/decoding ML models. In order to account for this noise, this study proposes three different synchronization capabilities between the client and trusted applications in the covert channel. These are synchronous, semi-synchronous, and asynchronous. Previously proposed PMU based covert channels deploy L1 and LLC cache PMU events. The latency of these events tends to be 100-1000 cycles limiting the bandwidth of these covert channels. We propose to use microarchitecture level events with latency of 10-100 cycles captured through PMU for covert channel encoding leading to a potential 100× higher bandwidth. This study conducts a series of experiments to evaluate the proposed covert channels under various synchronization models on a TrustZone supported Cortex-A processor using OP-TEE framework. As stated earlier, switch from signaling based on PMU cache events to PMU microarchitectural events leads to approximately 15× higher covert channel bandwidth. This proposed finer-grained microarchitecture event encoding covert channel can achieve throughput of the order of 11 Kbits/s as opposed to previous work's throughput of the order of 760 bits/s.
Topics: Computers; Humans
PubMed: 36236456
DOI: 10.3390/s22197354 -
PloS One 2023Tinnitus is a common problem in patients with a cochlear implant (CI). Between 4% and 25% of CI recipients experience a moderate to severe tinnitus handicap. However,...
BACKGROUND
Tinnitus is a common problem in patients with a cochlear implant (CI). Between 4% and 25% of CI recipients experience a moderate to severe tinnitus handicap. However, apart from handicap scores, little is known about the real-life impact tinnitus has on those with CIs. We aimed to explore the impact of tinnitus on adult CI recipients, situations impacting tinnitus, tinnitus-related difficulties and their management strategies, using an exploratory sequential mixed-method approach.
METHODS
A 2-week web-based forum was conducted using Cochlear Ltd.'s online platform, Cochlear Conversation. A thematic analysis was conducted on the data from the forum discussion to develop key themes and sub-themes. To quantify themes and sub-themes identified, a survey was developed in English with face validity using cognitive interviews, then translated into French, German and Dutch and disseminated on the Cochlear Conversation platform, in six countries (Australia, France, Germany, New Zealand, the Netherlands and United Kingdom). Participants were adult CI recipients experiencing tinnitus who received a Cochlear Ltd. CI after 18 years of age.
RESULTS
Four key themes were identified using thematic analysis of the discussion forum: tinnitus experience, situations impacting tinnitus, difficulties associated with tinnitus and tinnitus management. Among the 414 participants of the survey, tinnitus burden on average was a moderate problem without their sound processor and not a problem with the sound processor on. Fatigue, stress, concentration, group conversation and hearing difficulties were the most frequently reported difficulties and was reported to intensify when not wearing the sound processor. For most CI recipients, tinnitus seemed to increase when performing a hearing test, during a CI programming session, or when tired, stressed, or sick. To manage their tinnitus, participants reported turning on their sound processor and avoiding noisy environments.
CONCLUSION
The qualitative analysis showed that tinnitus can affect everyday life of CI recipients in various ways and highlighted the heterogeneity in their tinnitus experiences. The survey findings extended this to show that tinnitus impact, related difficulties, and management strategies often depend on sound processor use. This exploratory sequential mixed-method study provided a better understanding of the potential benefits of sound processor use, and thus of intracochlear electrical stimulation, on the impact of tinnitus.
Topics: Adult; Humans; Cochlear Implants; Tinnitus; Speech Perception; Cochlear Implantation; Hearing Loss
PubMed: 37079589
DOI: 10.1371/journal.pone.0284719 -
Nature Communications Dec 2022Tensor analytics lays the mathematical basis for the prosperous promotion of multiway signal processing. To increase computing throughput, mainstream processors...
Tensor analytics lays the mathematical basis for the prosperous promotion of multiway signal processing. To increase computing throughput, mainstream processors transform tensor convolutions into matrix multiplications to enhance the parallelism of computing. However, such order-reducing transformation produces data duplicates and consumes additional memory. Here, we propose an integrated photonic tensor flow processor (PTFP) without digitally duplicating the input data. It outputs the convolved tensor as the input tensor 'flows' through the processor. The hybrid manipulation of optical wavelengths, space dimensions, and time delay steps, enables the direct representation and processing of high-order tensors in the optical domain. In the proof-of-concept experiment, an integrated processor manipulating wavelengths and delay steps is implemented for demonstrating the key functionalities of PTFP. The multi-channel images and videos are processed at the modulation rate of 20 Gbaud. A convolutional neural network for video action recognition is demonstrated on the processor, which achieves an accuracy of 97.9%.
PubMed: 36577748
DOI: 10.1038/s41467-022-35723-2